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# EVEREX SYSTEMS, INC.
STEP 386 REV. G
Processor 80386DX
Processor Speed 16/20MHz
Chip Set C & T
Max. onboard DRAM 8MB
Cache 64/128KB
BIOS AMI
Dimensions 355mm x 304mm
I/O Options 32-bit external memory card
NPU Options 80387DX
(IMG) IMG 1
+------------------------------------------------------------+
| CONNECTIONS |
|------------------------------------------------------------|
| Purpose | Location |
|-----------------------------------------+------------------|
| 32-bit external memory card | S1 |
+------------------------------------------------------------+
+------------------------------------------------------------+
| USER CONFIGURABLE SETTINGS |
|------------------------------------------------------------|
| Function | Jumper/Switch | Position |
|---------------------------------+---------------+----------|
| ยป | Factory configured - do not | SW1 | Unknown |
| | alter | | |
+------------------------------------------------------------+
+------------------------------------------------------------+
| SYSTEM DRAM CONFIGURATION |
|------------------------------------------------------------|
| Size | Bank 0 | Bank 1 | Bank 2 | Bank 3 | W1 |
|------+-----------+----------+----------+----------+--------|
| 1MB | (4) 256K | NONE | NONE | NONE | Closed |
| | x 9 | | | | |
|------+-----------+----------+----------+----------+--------|
| 2MB | (4) 256K | (4) 256K | NONE | NONE | Closed |
| | x 9 | x 9 | | | |
|------+-----------+----------+----------+----------+--------|
| 4MB | (4) 1M x | NONE | NONE | NONE | Open |
| | 9 | | | | |
|------+-----------+----------+----------+----------+--------|
| 4MB | (4) 256K | (4) 256K | (4) 256K | (4) 256K | Closed |
| | x 9 | x 9 | x 9 | x 9 | |
|------+-----------+----------+----------+----------+--------|
| 8MB | (4) 1M x | (4) 1M x | NONE | NONE | Open |
| | 9 | 9 | | | |
|------+-----------+----------+----------+----------+--------|
| 16MB | (4) 1M x | (4) 1M x | (4) 1M x | (4) 1M x | Open |
| | 9 | 9 | 9 | 9 | |
|------------------------------------------------------------|
| Note:Banks 2 & 3, and W1 are located on the external |
| memory Board. |
+------------------------------------------------------------+
+------------------------------------------------------------+
| CACHE CONFIGURATION |
|------------------------------------------------------------|
| Size | Bank 0 | Bank 1 | TAG | Dirty Bit |
| | | | | (U38) |
|---------+-----------+-----------+---------+----------------|
| 64KB | (4) 16K x | NONE | (2) 16K | (1) 16K x 4 |
| | 4 | | x 4 | |
|---------+-----------+-----------+---------+----------------|
| 128KB | (4) 16K x | (4) 16K x | (2) 16K | (1) 16K x 4 |
| | 4 | 4 | x 4 | |
|------------------------------------------------------------|
| Note:Each Cache bank must be fully populated when its |
| corresponding DRAM bank is populated. |
+------------------------------------------------------------+
+------------------------------------------------------------+
| RESISTOR SIP CONFIGURATION |
|------------------------------------------------------------|
| Memory | RP28 | RP29 | RP30 | RP31 |
| Banks | | | | |
| installed | | | | |
|------------+-----------+-----------+-----------+-----------|
| Bank 0 | Installed | Open | Installed | Open |
|------------+-----------+-----------+-----------+-----------|
| Bank 0 & 1 | Open | Installed | Installed | Open |
|------------+-----------+-----------+-----------+-----------|
| Banks 0, | Open | Installed | Open | Installed |
| 1, 2, & 3 | | | | |
|------------------------------------------------------------|
| Note:Banks 2 & 3 are on the external memory card |
+------------------------------------------------------------+
(IMG) IMG 2
+------------------------------------------------------------+
| CACHE CONFIGURATION |
|------------------------------------------------------------|
| Size | Cache | Location |
|--------------+-------------------------+-------------------|
| 64KB | (8) 16K x 4 | Bank 2 |
|--------------+-------------------------+-------------------|
| 128KB | (8) 16K x 4 | Bank 2 & 3 |
|------------------------------------------------------------|
| Note:Each Cache bank must be fully populated when its |
| corresponding DRAM bank is populated. |
+------------------------------------------------------------+