UNIDENTIFIED
============

   TVGA9400CXI (DIP DRAM VERSION)

   Category                     Video                             
   Video Types Supported        XVGA                              
   Video Processor              Trident                           
   Highest Resolution Supported 1280 x 1024                       
   Data Bus Type                VESA local bus                    
   Memory Type                  DRAM                              
   Maximum Onboard Memory       2048KB                            

<gopher://bitreich.org/I/th99/v/U-Z/50590-1.png>
   

   +------------------------------------------------------------+
   |                        CONNECTIONS                         |
   |------------------------------------------------------------|
   |        Purpose        | Location |   Purpose    | Location |
   |-----------------------+----------+--------------+----------|
   | 15-pin analog video   |   CN1    | VESA feature |   CN2    |
   | port                  |          | connector    |          |
   +------------------------------------------------------------+

   +------------------------------------------------------------+
   |              MONITOR INTERLACE CONFIGURATION               |
   |------------------------------------------------------------|
   |               Setting               |          J7          |
   |-------------------------------------+----------------------|
   |>>   |          Interlaced           |        Closed        |
   |-----+-------------------------------+----------------------|
   |     |        Non-interlaced         |         Open         |
   +------------------------------------------------------------+

   +------------------------------------------------------------+
   |                  CPU CLOCK CONFIGURATION                   |
   |------------------------------------------------------------|
   |          Speed(MHz)          |             JX7             |
   |------------------------------+-----------------------------|
   |>>  |         <=33MHz         |            Open             |
   |----+-------------------------+-----------------------------|
   |    |         >33MHz          |           Closed            |
   +------------------------------------------------------------+

   +------------------------------------------------------------+
   |                   VESA LOCAL BUS TIMING                    |
   |------------------------------------------------------------|
   |          Setting           |              J1               |
   |----------------------------+-------------------------------|
   |>> |        Standard        |       Pins 2 & 3 closed       |
   |---+------------------------+-------------------------------|
   |   |       Alternate        |       Pins 1 & 2 closed       |
   +------------------------------------------------------------+

   +------------------------------------------------------------+
   |                    DMCLK CONFIGURATION                     |
   |------------------------------------------------------------|
   |           Frequency            |            J10            |
   |--------------------------------+---------------------------|
   |>>  |           80MHz           |           Open            |
   |----+---------------------------+---------------------------|
   |    |            MHz            |          Closed           |
   +------------------------------------------------------------+

   +------------------------------------------------------------+
   |                     DRAM CONFIGURATION                     |
   |------------------------------------------------------------|
   |      Size      |       Bank 0        |       Bank 1        |
   |----------------+---------------------+---------------------|
   |     1024KB     |    (8) 256K x 4     |        NONE         |
   |----------------+---------------------+---------------------|
   |     2048KB     |    (8) 256K x 4     |    (8) 256K x 4     |
   +------------------------------------------------------------+