NOTES: where possible I'll have references to Tricep.  I'll also
       have a section talking about how Tricep uses all the features
       of the bus and why the design needs the bus.  This will be at
       the end or perhaps a sidebar.  -bjg-





                      The IEEE-696/S-100 BUS



I 197  smal compan name MIT i Alburqurque N.M announce 
 produc i Popula electronic whic wa t establis th 
beginnin o th micr compute revolution  Th produc wa  
kit base upo  10 pi bu designe fo eas expansion  MIT 
publishe th specification fo th bu bringin abou wha i 
toda referrre t a th firs "ope architecture compute i  
worl the dominate b proprietar minicompute busses 

Th Altai bu a i wa know i thos day soo becam adopte 
b severa entreprenuer wh rallie aroun th Homebre Compute 
Clu i th sout bay  Wor o thes ne an excitin addition 
fo th Altai bu sprea beyon th clu an soo  marke wa 
born  Companie suc a Imsai Processo Technology Cromemc 
sproute u makin "plu compatable board fo wha no wa 
bein calle th "S-10 Bus ( ter usuall attribute t Roge 
Mellen  pricipa o Cromemco).

Althoug th S-10 bu signal wer fairl wel define (bein 
originall a extensio o th 808 uprocesso itself ther wa 
 tendanc o manufacturer t modif th meaning/name an 
timin o som o th line fo thei ow designs Som 
manufacturer eve adde thei ow signal t th unassigne 
lines  B 197 th compatabilit o product fro on 
manufacture wit product o othe manufacturer wa i seriou 
jeopardy.

I 1979 perhap thousand o design later som S-10 designer 
decide i wa tim t draf  specificatio fo th bu an 
presen i t th IEE fo professiona an publi inspection  
Georg Morrow o Morro Design wa chairma o th comitte 
and alon wit Howar Fullme (Morro Designs) Kell Elmquis 
(Intersystems an Davi Gustavso (Stanfor Linea Accelerator), 
hel meeting wit member o th S-10 desig communit t 
hamme ou  specificatio whic woul guarante  standar fo 
interfac an  futur growt pat a ne microprocessor becam 
available.

Afte man revision an  chang i chairmanshi (assume b So 
Libes th standar becam adopte b th IEE a th IEEE-696/S-
10 Standar i 1982.


                  I. Highlites of the S-100 bus

Amon th mos powerfu feature o th S-10 bs ar it' suppor 
o bot  bi an 1 bi board an it ful DM arbitration.

Unlik othe defact standar busse (Apple IB PC STD th S-
10 bu ha dedicate line allowin acces t bot 1 bi an  
bi devices  Th bu maste assert sXTR a th star o  
cycl an check fo SIXT fro th slav device  I th slav 
doesn' respond th acces i performe a a  bi operation  
Thi no onl allow suppor o olde  bi S-10 product bu 
allow th designe t optimiz th cost/performanc rati b 
usin th appropriat dat transfe siz t mee th application.
Fo instance i th Morro Tricep al CP acces t memor i 
performe usin 1 bi transfer wherea al DM I/Ϡ function 
ar performe i  bi mode  Th syste memor respond 
appropriately t th  requesting master device.

Direc Memor Acces (DMA i th process b whic  devic 
temporaril accesse th bu fo  particula proces an the 
relinquishe control  T mor clearl describ th proces a i 
applie t th bus th committe member labele th proces 
Temporar Maste Acces (TMA)  Althoug TM i no uniqu t th 
S-10 bus, TMA with arbitration is unique.

Arbitratio o th S-10 bu allow u t 1 TM device t  
shar th resource o th bus  I mor tha on TM device 
reques th bu simaltaneously th devic wit th highes 
priorit wil gai acces whil th devic wit lesse priorit 
mus suspen it reques unti i ha priority  Slo device ca 
the b intermixe wit fas device withou th overhea o 
softwar scheduling.  

Th Morro Trice fo instanc assign highes priorit t th 
DM har dis controlle becaus i i perhap th mos tim 
dependan elemen o  Uni syste an i share b al th 
processes  Termina I/ i  give  ver lo DM priorit sinc 
it function ar fa les tim critica an ar use dependant.




c) Ideal slave environment
   1) slaves can be either TMA devices with local CPU and resources
      or non TMA devices Morrow calls "smart memory devices".  Smart
      memory devices are usually dual ported memory, accessable on one
      side by all kinds of bus masters and on the other side by the
      local processor.  This local processor makes the device a "smart
      memory".		

d) Low cost (for a IEEE bus)
    1) The boards are relatively small in comparison to minicomputers
       but allow an average of 90 I.C.s on a 4 layer board.
    2) Onboard regulation of power reduces stringent power supply 
       requirements requiring only a three voltage filtered supply.
    3) Form factor allows small package (cite Cromemco 5 slot unit and
       Zenith Z-100)
    4 Wid availabilit o inexpensiv prototyp an bu debugging
       board fo system intergrators to add their own boards or devices.

e) Seperate I/O and Memory space
    1) allows full use of the 16 Mbyte memory space while still
       providing for 65536 I/O devices.  I/O devices need not be
       in the system memory map (unless desired)
	

f) Many operating systems, languages supported
     1) CP/M, (8080, 8086, 68000 versions) M/PM, CP/M Plus, Unix, Zenix,
        Genix, Idris, Regulus, Oasis, MS-DOS, Forth, UCSD P system, 
	Turbodos (both 8 and 16 bit),
     2) All the above operating systems virtually assure that a wide
	variety of language compilers and interpreters are available.
	It also assures availability of cross compilers, linkers and
	assemblers are available.

g) Open and well defined
     1 unlik proprietar buse o manufacturer whic hav ye 
        t establis themselve a  defact standard th S-10 bu 
        provide a wide open architecture.  It is defined by an IEEE
	standard and cannot change without formal proceedings.  (Cite
        the problems with the PC bus being 8 bit data width only and
	the problems faced by manufacturers trying to get true 16 bit
	devices to work correctly).

h) Copious amounts of hardware
	1) graphics (low, medioum, high and very high resolutions)
	2) emulators, analyzers, software developement products
	3) A/D and D/A (both low and high speed devices)
	4) speech 
	5) "real world" controller and monitoring devices
	6) controllers (SASI, SCSI, SMD, ST-506, Quik 02, IEEE-488,
	   9 TRACK TAPE, 8 and 5 inch Floppy)
	7) memory 64K low power CMOS to 2 Mbyte DRAM with ECC

i) Copious amounts of CPUs
	1) 8080, z80, 8085, 8088, 8086, 80186, 80286,
	   6800, 6809, 68000, 68010, 9900, NS16032, 

j) Networks
	 1) Ethernet, Northnet, Cnet, Arcnet

k) 10 available interrupt lines
         1) allow for an interrupt rich implementation for
	    environments such as Unix.



II. Advantages of an IEEE standard bus

a) cross manufacturer repsonsibility to adhere to standards
b) no bugs to come out of the woodwork during design or integration phases
   as a result of poorly defined or inadequately spec'd bus
c) upgradabl b committee concensu rathe tha a th whi o  
   singl manufacturer (IBM with the 8 bit PC bus).
e) wide supplier sources for products (card cages, power supplies, boards, 
   chassis etc.)




III. Uses of the bus (not in any order)

a) Graphics systems
b) Test equipment
c) Dedicated Controllers and monitors
d) Small business systems (single user very high performance)
e) Multi-use compute system (Unix, Turbodos Oasis MP/ )
f) Networked multiuser systems
g) Software and Hardware Developement systems
h) Scientific capture systems


IV. Problems

a) 24 bit address restriction
    1) this may be solved by use of the RFU (reserved for future use)
       lines on the bus and should be explored at which point 32 bit
       address space is required.  
b) 16 bit data path
     1) this can be solved by making all TMA or MASTER devices perform
	two 16 bit fetches similar to how current 16 bit devices work
	with 8 bit slaves.

c) synchronous
     1) the bus, since it originated with the 8080, was designed for
	synchronous devices.  This is not optimum for certain high
        speed, high performance designs.  Again an RFU line could be
	used to add this capability.

d) unregulated supply
     1) This makes power supplies simple but limits board space due to
	on board regulators.
     2) Cooling requirements for the onboard regulators is trickier.

    NOTE: This could be solved if the standard could include a provision
	  to run boards with regulated supplies. (Intersystems has done 
	  this already although it is not a standard)

V. Single board closed architecture vs. bus oriented open architecture debate
	a) cost, 
	b) flexability
	c) change CPU, change computer
	d) interchangeable parts
	e) upgradability
	f) power (AC)
	g) size and weight


VI. Tricep and how it uses the S-100 bus to its full potential

VII. Summary


Bob Groppo
Engineering Product Manager
Morrow Designs
San Leandro, Ca.
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