Subj : Re: TheA1200
To   : Nightfox
From : tenser
Date : Wed Dec 10 2025 01:01:18

On 08 Dec 2025 at 02:50p, Nightfox pondered and said...
 
 Ni>   Re: Re: TheA1200
 Ni>   By: tenser to Mortar M. on Tue Dec 09 2025 10:22 am
 Ni> 
 Ni>  MM>> FPGA is not emulation.
 Ni> 
 Ni>  te> Of course it is.  None of these machines, when they were still being
 Ni>  te> manufactured, shipped with a soft core on an FPGA.  They shipped with
 Ni>  te> regular, run-of-the-mill 68k series CPUs in silicon.
 Ni> 
 Ni>  te> FPGAs are programmed with a bitstream that makes them do, well, whate
 Ni>  te> the bitstream is programmed to do; in this case, perhaps, implement t
 Ni>  te> core of an MC68k CPU.
 Ni> 
 Ni>  te> Because the FPGA itself is a hardware device that provides programmab
 Ni>  te> logic, and not a general-purpose CPU that's running a program compile
 Ni>  te> that CPU's ISA that is emulating another machine, I can see how one m
 Ni>  te> not consider them "emulation" in the same category as a software emul
 Ni>  te> But this is, at best, arguing semantics.
 Ni> 
 Ni> While it might not be the same exact physical CPU, even though an FPGA is
 Ni> programmable, I feel like FPGA could be thought of as a hardware
 Ni> re-creation of the original.

A think I think you probably _could_ do is build a socket-compatible
carrier board for an FPGA that plugged into and acted like a drop-in
replacement for the original CPU.  But it's important to understand
that it's still not the original CPU; you could change out the
behavior of an instruction if you wanted.

 Ni> But even so, I've heard software emulation often isn't totally 100%
 Ni> accurate (maybe 99% though); compared to the original hardware, software
 Ni> emulation can have some issues that make it behave differently in some
 Ni> small cases (and corner cases).  I've heard FPGAs are (or can be)
 Ni> generally 100% compatible and don't have these issues though.

Retroswim mentioned timing, and that's probably one of the bigger
ones.  You _can_ build a cycle-accurate software implementation, but
it runs like a dog.  You may have a better time with an FPGA, since
it won't be constrained by _other_ software artifacts, but even then
you are only as bug-compatible as you spend the time and effort to be.

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