Subj : Re: TheA1200
To   : Nightfox
From : Retroswim
Date : Tue Dec 09 2025 11:51:26

 N> I've heard FPGAs are (or can be) generally
 N> 100% compatible and don't have these issues though.

They can be, it depends on the implementation. If the designer makes assumptions about how the target system works, they may not faithfully reproduce some edge cases.

For instance, the PC/XT core for MiSTer FPGA is /pretty good/, but can't run the Area 5150 demo, because the final effect depends on **SUBCYCLE** timing of 8237 DMA operations.

Lower level implementations of chips and systems use more FPGA cells than more abstract, higher-level implementations, and are more diffiult to do. It's a balancing act between the capacity of the target FPGA chip, and developer e/effort. 
Cheers,
RetroSwim

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