Subj : Re: TheA1200
To   : Gods69
From : tenser
Date : Sat Dec 06 2025 00:57:11

On 05 Dec 2025 at 08:11a, Gods69 pondered and said...

 Go> FPGA is also emulation. You must also program it in VHDL or Verilog
 Go> language. There is an "Human" factor, with this "BUG's" inside.

Trust me, there are bugs in silicon, too.  Usually quite a lot.  :-(

Many machines in the early days were "microcoded": that is, the CPU
instructions that programmers work in terms of are, themselves,
written in terms of even simpler "micro-ops".  Of course, the programmer
doesn't (generally) get to see those, but they're there, and sometimes
the micro programs have bugs.

The big innovation with RISC was that you didn't _need_ to do that,
and that if you cut out the ucode, you could make the CPU a lot faster.
The idea has come back in favor in recent years, though under the
hood things are mostly RISC.  Even systems like x86, with its grotesque
instruction set, are really RISC cores (really, dataflow CPUs) with an
instruction emulation layer plastered on top.

 Go> With FPGA you can do all the things in parallel, one bloc for the Clocks,
 Go> one for generating the display, one for Sound, another for CPU, etc...
 Go> They work individualy, no need to wait for each.
 Go> In software you have do to all the jogs sequencely. But with the CPU
 Go> more and more powerful the gap is narrowing.

That's not _quite_ true.  With multicore/SMT CPUs, you can have
hardware thread running each of those functions, in parallel with
the others.  Unfortunately, they can't be _quite_ independent: one
functional unit might need to wait for the result of another before
it can meaningfully proceed.  (Consider fetching instructions from
RAM before decoding them, and so on.)

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