To: Distribution
From: David Kahaner [ONRFE] kahaner@xroads.cc.u-tokyo.ac.jp
Re: Commercialization of PAX by Anritsu
29 April 1990

In earlier reports I mentioned that the MIMD computer PAX, developed at 
the University of Tsukuba by Professor Hoshino and colleagues was being
considered by the Anritsu Corporation for commercialization. On 1 April
1990, Anritsu announced that a 16 processor version of this machine is 
available. Anritsu already markets a scientific workstation, called 
DSV6440A, which has a 30 MFLOP peak performance. This is a Unix machine 
built around the MC68030 chip. An attached vector processor speeds up
floating point computations. The standard DSV6440A has a 320MB disk and
123MB cartridge tape unit. It comes with a 21-inch color monitor with 
1280x1024 dots resolution.  It can be networked via the usual networking 
interfaces. 

The vector processor is built into one triple height VME board. Users 
write programs in C or Fortran that run on the 68030, called "main 
programs", and other programs called "calculation programs" to describe 
algorithms to be performed on the vector processor. Programs for the 
latter are written in "FAUST-C". The calculation program is loaded into 
the vector processor memory by the main program. Data for calculation 
programs can come from vector registers (2MB) or from main memory.  The 
vector processor has a maximum claimed performance of 30 MFLOPS and 
scalar performance of 1.7 MFLOPS in 32 bit single precision.  In addition 
to arithmetic operations the vector processor has built in trig, 
exponential, square root, and logarithm functions.  

Only one vector processor board is mounted in the DSV6440A, but a 
parallel computer can be configured by connecting to a separate device in 
which a number of these boards are mounted. The board itself has an 
independent processing unit and a 4-channel interface for connecting 
other 32 bit data channels. A parallel computer can be configured by 
connecting via this route to a neighboring processing unit with data 
switching. If 16 such boards are connected the peak performance is thus 
16*30 or 480 MFLOPS. This additional collection of 16 boards has now been 
packaged by Anritsu. The ensemble unit is named DSV6450.  

Below is a simple example of programming in FAUST-C for the core portion 
of an SOR (Successive Over Relaxation) calculation. It is very close to 
the program that I displayed in describing QCD PAX and illustrates the 
vector instructions.

for (iter=0; iter<ITERMAX; iter++){
   for (rb=0; rb<2; rb++){
      getorg();
      vfor (k=orgnw; k<MSEE; k+=2){
         u[k]=omg4*(u[k-1]+u[k+1]+u[k-M12]+u[k+M12]+q[k])+omg1*u[k];
      } with;
      vfor (m1=orgc; m1<M1; m1+=2){
        u[m1+1]=ZERO;
        u[m1+MSWS]=ZERO;
      } with;
      vfor (m2=orgc; m2<M2; m2+=2){
        u[M12*m2+M12]=ZERO;
        u[M12*m2+MNEE]=ZERO;
      } with;
   }
}

This is one of the first entirely Japanese parallel processors. It has 
all the capabilities that I reported on in Hoshino's PAX computer, plus, 
now the backing of a substantial company. Anritsu has arranged for 
demonstrations of the machine in several Japanese cities; unfortunately I 
missed the one in Tokyo.  However, Anritsu is not well known as an 
advanced computer manufacturer, and there is speculation here that the 
responsibilities for building this machine were subcontracted out. At 
this time I have no pricing information. Anritsu can be reached at 10-27, 
Minamiazabu 5-chome, Minato-ku, Tokyo 106 JAPAN; phone: 81-3-446-1111; 
fax: 81-3-442-0235.  

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